1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a Dynamic Random Access Memory (DRAM) in which a memory cell stores information in a capacitor in a form of electric charges. More particularly, the present invention relates to a dynamic random access memory in which a bit line is structured of sub-bit lines to which memory cells are connected, and a main bit line to which the sub-bit lines are connected.
2. Description of the Background Art
FIG. 18 schematically shows a structure of a memory cell array portion of a conventional dynamic random access memory. The structure shown in FIG. 18 is disclosed in, for example, Japanese Patent Laying-Open No. 62-298089. In FIG. 18, a structure of a portion is shown relating to memory cells on one column.
Referring to FIG. 18, memory cells MC are divided into N groups 10A to 10N. Each memory cell MC includes a transistor 7 and a capacitor 8 having one electrode connected to transistor 7.
Sub-bit lines 20A, 30A, . . . are located corresponding to each of N memory cell groups. In FIG. 18, only sub-bit lines 20A and 30A in memory cell group 10A are shown. Transistors 7 of memory cells MC are alternately connected to sub-bit lines 20A and 30A. The other electrodes (electrodes not connected to transistors 7) of capacitors 8 of memory cells MC are connected to a cell plate line 52 in common. A constant voltage Vcp is transmitted to cell plate line 52.
Main bit lines 2 and 3 are arranged in common for memory cell groups 10A to 10N. Switch circuits 5A to 5N and 6A to 6N are provided corresponding to memory cell groups 10A to 10N.
Switch circuits 5A to 5N connect sub-bit lines 20A, 30A, . . . of corresponding memory cell groups to main bit lines 2 and 3 in response to block select signals .phi.SA to .phi.SN from block selecting circuits 17A to 17N.
Switch circuits 6A to 6N disconnect sub-bit lines 20A, 30A, . . . of corresponding memory cell groups from a constant voltage VD supply transmission line 4 in response to block select signals /.phi.SA to /.phi.SN applied through inverter circuits 15A to 15N.
Word lines 9-1 to 9-M, . . . are arranged corresponding to transistors 7 of memory cells MC in the direction crossing main bit lines 2 and 3 (sub-bit lines 20A, 30A, . . . ). In FIG. 18, only word lines 9-1 to 9-M in memory cell group 10A are shown. A row select signal from a row decoder 16 is applied to word lines 9-1 to 9-M. Row decoder 16 decodes row address bits (not shown), and brings one word line to a selected state. Block selecting circuits 17A to 17N bring a block select signal to an active state only for a memory cell group including the selected word line.
A peripheral circuit 18 is provided for main bit lines 2 and 3, which includes a sense amplifier, an IO gate for transmitting a sense amplifier output onto an internal data bus, and the like. Operation will now be described.
In a stand-by state, outputs of row decoder 16 and block selecting circuits 17A to 17N are all at a low level. Accordingly, switch circuits 5A to 5N are in an off state, and switch circuits 6A to 6N are in an on state. In memory cell groups 10A to 10N, sub-bit lines 20A, 30A, . . . are precharged to a constant reference voltage VD through switch circuits 6A to 6N. Cell plate line 52 is normally supplied with a constant voltage Vcp.
In access, an access start instructing signal such as a row address strobe signal /RAS and a chip enable signal /CE is externally applied. In response to the access start instructing signal, an internal address signal is generated (according to an externally applied address signal), to be applied to row decoder 16 and block selecting circuits 17A to 17N. Row decoder 16 decodes the applied internal address signal, and generates a signal selecting one word line. In order to select a memory cell group, block selecting circuits 17A to 17N bring a block select signal for a memory cell group including the selected word line to an active state at this time. Now, assume that word line 9-1 is selected.
First, a signal .phi.SA of block selecting circuit 17A attains a high level, and block select signal /.phi.SA attains a low level. Accordingly, switch circuits 5A and 6A are brought to on and off states, respectively, and sub-bit lines 20A and 30A are connected to main bit lines 2 and 3. Sub-bit lines 20A and 30A are disconnected from constant voltage VD, and brought to a floating state.
When the potential of word line 9-1 rises to a high level, transistor 7 of memory cell MC is brought to an on state, and electric charges stored in capacitors 8 are transmitted onto sub-bit line 20A. The potential change on sub-bit line 20A is transmitted onto main bit line 2 through switch circuit 5A. Sub-bit line 30A maintains a precharge potential VD since electric charges of memory cell capacitors 8 are not transmitted onto sub-bit line 30A.
Then, the sense amplifier included in peripheral circuit 18 is brought to an active state, to amplify potential difference between main bit lines 2 and 3 and between sub-bit lines 20A and 30A. In reading operation, the IO gate (included in peripheral circuit 18) is selected in response to a column select signal from a column decoder (not shown), and data amplified by the sense amplifier included in peripheral circuit 18 is transmitted onto internal data bus. In writing operation, write data is transmitted through the internal data bus in this state. The potentials of main bit lines 2 and 3 and sub-bit lines 20A and 30A attain levels corresponding to the write data.
When one memory cycle is completed, the potential of the selected word line 9-1 falls to a low level, and then block select signals .phi.SA and /.phi.SA attain low and high levels, respectively. Sub-bit lines 20A and 30A are again connected to constant voltage VD supply transmission line 4, the potentials of which attain a level of constant voltage VD.
In non-selected memory cell groups (memory cell groups not including the selected word line) 10B to 10N, switch circuits 6B to 6N are in an on state, and switch circuit 5B to 5N are in an off state. The sub-bit lines are maintained at a constant voltage VD level. The sub-bit lines are arranged between cell plate line 52 and main bit lines 2 and 3.
Even when cell plate line 52 is normally supplied with constant cell plate voltage Vcp, sub-bit lines in the non-selected memory cell groups have the potentials retained at constant voltage VD. Therefore, cell plate line 52 is shielded from main bit lines 2 and 3 by those sub-bit lines, resulting in reduction of a parasitic capacitance between main bit lines 2 and 3 and cell plate line 52. Cell plate line 52 is capacitive-coupled mainly with the sub-bit lines. The potential of each of the non-selected sub-bit lines is fixed, reducing capacitive noise of the bit line (sub/main bit lines).
As a semiconductor memory device is made large in storage capacity, the number of memory cells arranged on one column increases. The size of a memory cell becomes small, and a capacitance value of capacitor 8 becomes small accordingly. When a capacitance value of memory cell capacitor 8 becomes small, the amount of electric charges stored therein is decreased, which makes it difficult to provide a sufficient potential change to each of main bit lines 2 and 3. Referring to FIGS. 19A through 20B, the amount of potential change of each of main bit lines 2 and 3 will be found in the following.
Consider the precharge state as shown in FIG. 19A. Assume that a parasitic capacitance of each of main bit lines 2 and 3 is Cmb, and a parasitic capacitance of each of sub-bit lines 20A and 30A is Csb. Assume that a capacitance value of memory cell capacitor 8 is Cs. For facilitation of description, assume that precharge potentials of main bit lines 2, 3 and sub-bit lines 20A, 30A are all VD=Vcc/2 in the precharge state, wherein Vcc denotes an operating power supply voltage. Assume that the cell plate potential Vcp of memory cell capacitor 8 is also equal to Vcc/2.
As is clear from an electric equivalent circuit shown in FIG. 19B, charges Qmb stored in each of main bit lines 2 and 3, charges Qsb stored in each of sub-bit lines 20A and 30A, and charges Qs stored in memory cell capacitor 8 are expressed by: EQU Qmb=VD.multidot.Cmb=Vcc.multidot.Cmb/2, EQU Qsb=VD.multidot.Csb=Vcc.multidot.Csb/2, EQU Qs=(V-Vcp).multidot.Cs=(V-Vcc/2).multidot.Cs
where V is a write voltage to a memory cell, and V=Vcc when data at a high level is written, and V=0 when data at a low level is written.
As shown in FIG. 20A, in read operation of memory cell data, sub-bit line 20A is connected to main bit line 2, and memory cell capacitor 8 is connected to sub-bit line 20A. Although sub-bit line 30A is connected to main bit line 3, sub-bit line 30A has no memory cell capacitors connected thereto. In this state, as shown in FIG. 20B, potentials of memory cell capacitor 8, sub-bit line 20A, and main bit line 2 attain a read potential VR. In this state, charges Qmb', Qsb', and Qs' stored in main bit line 2, sub-bit line 20A, and memory cell capacitor 8 are expressed by: EQU Qmb'=VR.multidot.Cmb, EQU Qsb'=VR.multidot.Csb, EQU Qs'=(VR-Vcp).multidot.Cs
Since the total amount of electric charges does not change between the precharge state and the reading operation of memory cell data, the following expression is obtained based on the principle of conservation of charges: EQU Qmb+Qsb+Qs=Qmb'+Qsb'+Qs',
By substituting respective values in the above expression, the following expression is obtained: EQU (Cmb+Csb-Cs).multidot.Vcc/2+V.multidot.Cs=(Cmb+Csb+Cs).multidot.VR-Cs.multi dot.Vcc/2
By changing the above expression, the following expression is obtained: EQU VR={(Cmb+Csb).multidot.Vcc/2+V.multidot.Cs}/(Cmb+Csb+Cs)
The potential of main bit line 3 is at a level of Vcc/2 in the precharge state. Therefore, the potential difference (read voltage) .DELTA.V between main bit lines 2 and 3 in reading data is given by: EQU .DELTA.V=VR-Vcc/2={(V-Vcc/2).multidot.Cs/(Cmb+Csb+Cs)}
A write voltage V of a memory cell in restoring operation or in writing data is Vcc or 0. Therefore, the following expression is obtained: EQU .DELTA.V=.+-.Cs.multidot.Vcc/(2.multidot.(Cmb+Csb+Cs)) (1)
The number of memory cells connected to a sub-bit line is smaller as compared to the case of a bit line of an ordinary non-hierarchical structure. In addition, the length of the sub-bit line becomes shorter. Therefore, the parasitic capacitance Csb becomes smaller as compared to the case of a bit line of a non-hierarchical structure. However, main bit lines are provided, and since the main bit lines extend over one entire column, the interconnection capacitance exists. Therefore, it is desired from the standpoint of high integration to increase the read voltage as much as possible even in such a hierarchical bit line structure.
The pitch of a main bit line becomes narrower with high integration. One sub-bit line pair is located for a main bit line pair in the row direction. Since the interval between sub-bit lines is the same as the interval between main bit lines, it is necessary to locate two memory cells between the sub-bit line pair. Therefore, as the pitch of the sub-bit line becomes smaller, it becomes extremely difficult to layout memory cells.
In order to alleviate the pitch condition of the sub-bit line, it is considered to structure the main bit line and the sub-bit lines in interconnection layers at different levels. Also in this case, a switching circuit is required for connecting the sub-bit lines to the main bit line structured in an interconnection layer at a different level. The switching circuit operates in response to a block select signal. From the standpoint of layout, it is preferred to repeat the same pattern in terms of area efficiency, facilitation of layout, and the like. Therefore, it is preferred to locate such a switch for selection of a memory cell group without affecting negatively the repetition pattern in the memory cell array.